Semiconductor memory devices may be divided into volatile memory devices, e.g., dynamic random access memory (DRAM) or static random access memory (SRAM), and non-volatile memory devices, e.g., flash memory devices. The degrees of integration, operating speeds, and capacitances of the semiconductor memory devices have been greatly improved due to expanding application thereof.
As the degree of integration of a semiconductor memory device is increased, a finer pattern or a smaller contact size may need to be formed and, thus, a photolithography process for forming the finer pattern or the smaller contact size may be faced with limits of resolution. Accordingly, a process of forming a contact included in the semiconductor memory device may include a self-aligned contact process where a contact hole is formed using an etch selectivity difference between an insulation interlayer and element structures, e.g., bit line structures and word line structures.
On the other hand, recently, research has been carried out on a word line having a buried gate structure where a gate electrode is buried under an upper surface of a substrate. Because the buried gate electrode is completely buried within a recess portion that is formed in the substrate, a patterning process for forming the gate electrode may not be required. Therefore, the gate electrode may be easily formed using metal material. Further, a spacer is not formed on sidewalls of the gate electrode, to thereby increase a contact area formed on both sides of the gate electrode.
In a formation of a cell of the memory device, if the buried electrode is used for a gate that is provided as a word line, because the gate electrode does not protrude from the surface of the substrate, the self-aligned contact process may not be performed. Thus, when a photo-misalignment occurs in a photolithography process, the contact may not be formed to be precisely aligned.
When the buried gate electrode is used to manufacture a DRAM device, it may be difficult to form pad contacts that are respectively connected to a bit line contact and a storage node contact on source/drain regions on both sides of the gate electrode, because the self-aligned contact process is not performed. Therefore, when the buried gate electrode is used, the bit line contact and the storage node contact may be formed to extend directly to the active substrate without using the pad contacts.
When the bit line contact and the storage node contact are formed without the pad contacts, the height of each of the contacts is greatly increased. Therefore, a not-open failure that a contact portion of the substrate is not exposed by the contact hole in an etch process for forming the contacts may occur frequently. Further, in a process for forming the storage node contact, a time of an etch process for forming the contact may be greatly increased. Accordingly, a sidewall spacer of the previously formed bit line structure may be excessively etched to cause a short failure between the bit line and the storage node contact.